/* Important! This is NOT a part of HERA project!
 * It's just an example to watch how hyperterminal operates
 */

module hyperterm
(
input  wire clk_48,
input  wire rst_,
output reg  tx,
input wire rd,
input  wire dtr,
output wire dsr,
output wire cd,
input  wire rts,
output wire cts,
output reg [7:0] buffer,
output reg clk2
);

assign dsr = dtr;
assign cd  = dtr;
assign cts = rts;



reg [13:0] count2;

reg [13:0] count;

always @ ( posedge clk_48, negedge rst_ )
if ( ~rst_ )
	count <= 14'd0;
else
if ( count == 14'd9999 )
	count <= 14'd0;
else
	count <= count + 1'd1;
	
always @ ( posedge clk_48, negedge rst_ )
if ( ~rst_ )
	count2 <= 14'd0;
else
if ( count2 == 14'd999 )
	count2 <= 14'd0;
else
	count2 <= count2 + 1'd1;

reg        clk;

always @ ( posedge clk_48, negedge rst_ )
if ( ~rst_ )
	clk <= 1'b0;
else
if ( count == 14'd9999 )
	clk <= ~clk;
	
always @ ( posedge clk_48, negedge rst_ )
if ( ~rst_ )
	clk2 <= 1'b0;
else
if ( count2 == 14'd999 )
	clk2 <= ~clk2;

reg  [3:0] tx_count;

/*reg  [7:0] msg[15:0];

always @ (posedge rst_)
begin
	msg[00] = "H";
	msg[01] = "e";
	msg[02] = "l";
	msg[03] = "l";
	msg[04] = "o";
	msg[05] = ",";
	msg[06] = "W";
	msg[07] = "o";
	msg[08] = "r";
	msg[09] = "l";
	msg[10] = "d";
	msg[11] = "!";
	msg[12] = "U";
	msg[13] = "P";
	msg[14] = "3";
	msg[15] = 8'ha;
end

reg  [4:0] char_num;

always @ ( posedge clk, negedge rst_ )
if ( ~rst_ )
	char_num <= 5'd0;
else
if ( tx_count == 4'd9 )
	char_num <= char_num + 1'd1;

wire [7:0] char = msg[char_num];
*/
always @ ( posedge clk, negedge rst_ )
if ( ~rst_ )
	tx_count <= 4'd0;
else
if ( tx_count == 4'd9 )
	tx_count <= 4'd0;
else
if ( ~rd | ( tx_count != 4'd00 ) )
	tx_count <= tx_count + 1'b1;

always @ ( posedge clk ) begin
/*if ( ~rst_ )
	tx <= 1'b1;
else*/
buffer[0] <= (tx_count == 4'd0)? 1'b0 :
			 (tx_count == 4'd1)? rd:
			 buffer[0];
buffer[1] <= (tx_count == 4'd0)? 1'b0 :
			 (tx_count == 4'd2)? rd:
			 buffer[1];
buffer[2] <= (tx_count == 4'd0)? 1'b0 :
			 (tx_count == 4'd3)? rd:
			 buffer[2];
buffer[3] <= (tx_count == 4'd0)? 1'b0 :
			 (tx_count == 4'd4)? rd:
			 buffer[3];
buffer[4] <= (tx_count == 4'd0)? 1'b0 :
			 (tx_count == 4'd5)? rd:
			 buffer[4];
buffer[5] <= (tx_count == 4'd0)? 1'b0 :
			 (tx_count == 4'd6)? rd:
			 buffer[5];
buffer[6] <= (tx_count == 4'd0)? 1'b0 :
			 (tx_count == 4'd7)? rd:
			 buffer[6];
buffer[7] <= (tx_count == 4'd0)? 1'b0 :
			 (tx_count == 4'd8)? rd:
			 buffer[7];
end
/*case ( tx_count )
	4'd01:   buffer[0] <= rd;
	4'd02:   buffer[1] <= rd;
	4'd03:   buffer[2] <= rd;
	4'd04:   buffer[3] <= rd;
	4'd05:   buffer[4] <= rd;
	4'd06:   buffer[5] <= rd;
	4'd07:   buffer[6] <= rd;
	4'd08:   buffer[7] <= rd;
	4'd00:	 buffer <= 8'd0;
	default: 
endcase
*/
endmodule